CST 334 Week 4

This week in CST 334 felt like a deep dive into the core mechanics of how an operating system manages memory. The readings, from paging and TLBs to swapping, all built upon one another and helped me understand virtual memory. Starting with OSTEP 18, the concept of paging immediately clicked as a much more elegant solution than the segmentation methods we looked at previously. Breaking both the virtual address space and physical memory into fixed-size pages seems like such a straightforward way to avoid external fragmentation and simplify allocation. However, the performance cost of requiring an extra memory access for every address translation was an obvious drawback, which made the introduction of the Translation Lookaside Buffer (TLB) easier to understand. Understanding the TLB as a specialized hardware cache that speeds up these translations was a key insight. Then, OSTEP 20 on multi-level paging addressed the next big question I had: how does the OS handle the massive page tables required for modern 64-bit address spaces without using up all of RAM just to store the tables themselves? The idea of creating a "page table of page tables" is clever, and seeing how it saves space was enlightening.

While the readings laid a solid theoretical foundation, the hands-on labs were where these concepts were truly put to the test. It’s one thing to understand the theory of how a virtual address is broken down into a page number and an offset, but it's another thing entirely to manually trace that translation through a multi-level page table to find the final physical address.